1. Field of the Invention
The present invention relates generally to linewidth measurement methods employed when fabricating microelectronic products. More particularly, the present invention relates to linewidth standard based linewidth measurement methods employed when fabricating microelectronic products.
2. Description of the Related Art
Significant in the microelectronic product fabrication art is a need to monitor and control dimensions (i.e., critical dimensions) of patterned layers and patterned structures which are employed when fabricating microelectronic products. Such monitoring and control of dimensions of patterned layers and patterned structures is in turn important insofar as performance characteristics of microelectronic products are often defined at least in part by dimensional characteristics of patterned layers and patterned structures which comprise the microelectronic products.
While patterned layer dimension monitoring and control is thus desirable and often essential in the microelectronic product fabrication art, such monitoring and control is nonetheless not entirely without problems. In that regard, it is often difficult to accurately monitor and control linewidth when fabricating microelectronic products.
It is thus desirable in the microelectronic product fabrication art to accurately monitor and control linewidth when fabricating microelectronic products.
It is towards the foregoing object that the present invention is directed.
Various apparatus and methods have been disclosed in the microelectronic product fabrication art for monitoring linewidth when fabricating microelectronic products.
Included but not limiting among the apparatus and methods are those disclosed within: (1) Archie et al., in U.S. Pat. No. 5,969,273 (an apparatus and method for critical dimension linewidth monitoring when fabricating microelectronic products by employing an edge width determination for a patterned layer); (2) Blatchford et al., in U.S. Pat. No. 6,258,610 (a method for patterned layer dimension determination within a microelectronic product while employing an auto-correlation); and (3) Choo et al., in U.S. Pat. No. 6,373,053 (a method for analyzing scanning electron microscopy measurements such as to determine scummed or closed structures or features within microelectronic products).
The teachings of each of the foregoing references are incorporated herein fully by reference.
Desirable in the microelectronic product fabrication art are additional apparatus and methods for linewidth monitoring when fabricating microelectronic products.
It is towards the foregoing object that the present invention is directed.